• Youngwoo Park, Senior Tech GM

    Tokyo Electron Korea

    Process and Equipment Development for Advanced Technology at Tokyo Electron Limited

    CV
  • Sungmin Huh, Manager

    ASML Korea

    Title: Semiconductor Scaling for the Next Generation Enabled by Lithography

    CV
  • Yuchul (Mike) Hwang, VP of Technology

    Samsung Electronics Co., Ltd. Device Solution (Memory Division)

    Title: Reliability Readiness of Memory Devices for Immersion Cooling Environments

    CV
  • Ki-ill Moon, VP

    SK Hynix Inc.

    Title: Interconnection Technology in Memory for Generative AI Era

    CV

Youngwoo Park, Senior Tech GM

Tokyo Electron Ltd.

Title: Process and Equipment Development for Advanced Technology at Tokyo Electron Limited


Abstract

Looking at the recent direction of device evolution, DRAM is pursuing an extreme extension of 2DDRAM and NAND is accelerating stacking technology. In addition, Logic is accelerating the introduction of GAA and BSPDN. I would like to talk about the device development strategy and roadmap TEL estimates in DRAM, NAND, and Logic. Next, I would like to explain the process and equipment development strategy of TEL for the next generation technology. Litho, Etch, Deposition, Cleaning, and BEOL with Wafer Bonding (3D Architecture) will be reviewed.

Biography

I got Ph.D. at UCLA EE.
And I worked at Samsung Electronics for about 29 years.
I was also a professor in Korea University EE for 2 years.
I have been working at Tokyo Electron Korea since 2018.

Sungmin Huh, Manager

ASML Korea

Title: Semiconductor Scaling for the Next Generation Enabled by Lithography


Abstract

For more than 50 years, Moore's Law has driven the steady shrink of feature sizes for integrated circuits. With this technology, semiconductor technology can continuously drive to increase performance and reduce power for semiconductors. Opportunities arise to extend Moore’s law through a combination of dimensional scaling with EUV lithography, and improvement of device and system level. In this paper, we examine trends in lithography development status that drive scaling-not just in pure dimensions but also associated variability control. Then updating ASML’s EUV roadmap both for 0.33NA and 0.55NA (High-NA) EUV systems, with the latest development status. And finally, it will provide the potential path forward beyond High-NA EUV to meet Moore’s law for next decades.

Keywords: Lithography, Moore’s law, Scaling, DUV, EUV lithography, High NA EUV lithography

Biography

Sungmin Huh is the field marketing manager in ASML Korea. He received M/S degrees in Material Science & Engineering from Hanyang University in 2002, He joined Samsung Electronics and worked for EUV mask development in Mask Development Team of Semiconductor R&D center for 20 years. He worked as project leader at SEMATECH from 2008~2010 for EUV mask infrastructure, and worked as committee of BACUS steering committee. He moved to ASML Korea in 2023 and currently working on field marketing on corporate strategy, foundry business, and customer impact.

Yuchul (Mike) Hwang, VP of Technology

Samsung Electronics Co., Ltd.Device Solution (Memory Division)

Title: Reliability Readiness of Memory Devices for Immersion Cooling Environments


Abstract

Immersion cooling is an emerging and ever-expanding cooling technique used in various industries, particularly in high performance computing data centers that require efficient cooling for electronics and computer system. The cooling method for energy saving of datacenter is changing from existing air cooling to liquid and immersion cooling, and immersion cooling is a method of cooling directly by soaking in a non-conductive fluid material called coolant, and is receiving high density, high efficiency, and green (ESG) solution because it can be used with optimal power usage efficiency (PUE), high operational stability and semi-permanent use.

This new operational environmental change is certain to have clear benefits to data centers in terms of performance and operational cost. However when it comes to the reliability of memory devices, which is essential parts of data center, immersion cooling can have both positive and negative impact and the risk from this new environment has not been properly discussed and organized yet

In this talk, we will figure out and suggest which reliability concerns emerge and what should be considered/ prepared in advance, and how to evaluate the risk due to immersion cooling environment which is an inevitable choice in the future: in terms of thermal, mechanical, chemical, and even cosmic ray point of view. In addition, we will also discuss the memory device’s reliability risks to the change of air cooling environment trend and how to evaluate them.

Keywords: memory device, immersion cooling, air-cooling, reliability, liquid cooling

Biography

Dr. Yuchul (Mike) Hwang is currently VP of technology at Samsung Electronics, semiconductor division since 2019 and working on quality and reliability assessment of semiconductor devices in terms of package/wafer level. He received his Ph.D. degree in mechanical/material engineering from the University of Maryland at College Park and he research interests includes transistor and metallization reliability modeling, EMI, ESD, package level/board level reliability, and M.L. based reliability prediction. He has published over 50 journal and conference papers in the field of electronics quality & reliability.

Ki-ill Moon, VP

SK Hynix Inc.

Title: Interconnection Technology in Memory for Generative AI Era


Abstract

It is expected that memory usage will exponentially increase according to the explosive interest in generative AI and its expanded application. Along with this industrial trend, the demand for memory products with high bandwidth, high capacity, and better power efficiency is increasing. In this paper, we would like to introduce key packaging technology of a high bandwidth memory (HBM) and its future challenges which SK Hynix has led its technology as world 1st and world best performance.

Keywords: Advanced Packaging, HBM, MR-MUF, TSV

Biography

Mr. Moon is currently working as a technical leader (VP) for package technology development, in SK hynix. He has more than 25 years’ experience in semiconductor package development including wafer level, flip chip and 2.5D/ 3D packaging as well as conventional package. He previously served as package development project manager for package material, process and equipment until assuming his current role in 2022. And he has been involved in the development and mass production of NAND Flash, DRAM/ Mobile, MCP, RDL, Flip chip, WLCSP and TSV. He received degree in chemistry from Sogang University in Seoul, Korea


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