ISMP 2025

Abstract

• Heterogeneous chiplets introduction in advanced packaging has offered a very viable solution to AI products developments in a way that die-to-die interconnect platform provides similar system performance to SoC and various options for power delivery and signal integration have been explored per product design. Looking at 2.5D/3D advanced packaging for AI applications from the system perspective can lead us to see which areas for developments should be paid attention to. AI applications are eventually destined to the data center where all necessary data transactions are made to meet end users’ tasks. Especially in the AI area, compute and memory are 2 pillars for performance. There will be a discussion related to those 2 nearest neighbors such as die-to-die interconnection, power delivery, thermal concerns & possible solutions, and etc.

Biography

• 1981-1986 Korea University Bachelor's degree in Physics and Master's degree in Statistical Physics
• 1986-1993 MS & Ph.D. at Case Western Reserve University
• 1996-2015 Amkor Technology Inc., CTO/ Head of WW Procurement/WW Operation/Head of Business Unit
• 2016-2018 Lam Research Corporation, VP of Advanced Packaging
• 2018-2023 JCET Group, CEO/ CTO
• 2023-2025 Intel Corporation, Assembly & Test Tech Development GM/SVP

Abstract

• The semiconductor industry is entering a new era where system-level performance, energy efficiency, and heterogeneous integration are increasingly defined not only by transistor scaling but also by innovations in advanced packaging. Its role is shifting from ensuring connectivity to directly defining system level performance, giving rise to the concept of the system package. In this vision, packaging is no longer limited to interconnection but becomes a platform that integrates logic, memory, analog, photonics, and domain-specific accelerators into a single, coherent system. Traditional scaling is reaching physical and production cost limits, shifting the focus toward three-dimensional integration, chiplet based architectures, and novel interconnect technologies. These trends are driving the convergence of logic, memory, analog, and photonics within highly integrated packages that promise unprecedented performance and flexibility. At the same time, new materials, thermal management approaches, and reliability solutions are being developed to overcome fundamental bottlenecks in power delivery and heat dissipation. Looking forward, advanced packaging will play a central role in enabling next-generation applications such as high-performance computing and on device artificial intelligence applications. This talk will provide an overview of current state-of-the-art packaging technologies, highlight key challenges that must be addressed, and explore emerging directions, including heterogeneous integration, wafer-level fan-out, and hybrid bonding, that are poised to transform the semiconductor ecosystem. By examining both the technical and ecosystem perspectives, we will discuss how advanced packaging innovation can shape the next era of computing, artificial intelligence, and high-speed communication.

Biography

• • Corporate VP, Package Development Team, Semiconductor R&D Center, Samsung Electronics, 2017 ~ present
• • TD Engineering Manager, ATTD, Intel Corporation, AZ, USA 2004 ~ 2017
• • Research Faculty Associate, Arizona State University, USA 2001 ~ 2004
• • Ph. D. Material Science & Engineering, Yonsei University, Seoul, Korea 2001

Abstract

• Artificial intelligence is redefining performance requirements across data centers, mobile, automotive, and edge applications. To deliver the bandwidth, power efficiency, and scalability that AI demands, the semiconductor industry is increasingly turning to advanced packaging — including heterogeneous integration, chiplet architectures, and high-density interconnects.
  
  Yet the success of these packaging innovations hinges on one critical factor: equipment capability. From fine pitch bonding and inter-die gap fill to shape management and panel-level processing, advanced equipment determines whether new architectures can move beyond R&D into reliable, high-volume manufacturing.
  
  This presentation shares an equipment maker’s perspective on how to accelerate the adoption of advanced packaging for AI:
  • Trends in AI-driven packaging requirements and their implications for manufacturing.
  • Key equipment challenges and innovations enabling high-density integration.
  • Scalable and versatile platforms that bridge feasibility and production.
  • Collaborative approaches to shorten time-to-market and reduce risk.
  
  As a leading international equipment supplier, we view advanced packaging not only as the next step in semiconductor evolution, but as a manufacturing challenge that requires robust, versatile, and reliable equipment solutions. By aligning technology innovation with production readiness, equipment innovation becomes the true enabler of AI’s next leap.

Biography

• Lee, Chee Ping is a Managing Director at Lam Research, with over 20 years of expertise in the semiconductor industry, specifically focusing on advanced packaging and heterogeneous integration. He spearheads the technical marketing efforts for Lam's wafer and panel-level equipment solutions. Lee Chee Ping's insights have been shared at various prestigious advanced semiconductor packaging conferences.



• Lee, Chee Ping received his M.Sc in Financial Engineering and B.Eng in Chemical Engineering from National University of Singapore.

Abstract

• Multi-chip integration has become a standard approach in AI training and is rapidly gaining traction in edge learning applications. Leveraging 2.5D and 3D IC architecture enables substantial improvements in energy efficiency and latency by optimizing inter chip data transfer. At the core of this transformation lies the automation of design and simulation for heterogeneous AI chips, shifting from manual engineering to algorithm driven methodologies. This evolution is being accelerated by advanced electronic design automation (EDA) tools powered by AI. My research group develops novel AI driven algorithms that enhance or replace traditional design automation techniques, with a focus on enabling next generation heterogeneous AI systems. In this talk, I will present our recent innovations and explore the critical challenges that lie ahead in applying AI algorithms to EDA for high performance AI chip design.

Biography

• Dr. Sung Kyu Lim is Dean’s Professor of Electrical and Computer Engineering at the University of Southern California, joining in Fall 2025 after over two decades at Georgia Tech. He received his B.S., M.S., and Ph.D. in Computer Science from UCLA. His research focuses on the architecture, design, and electronic design automation (EDA) of 2.5D and 3D integrated circuits, with over 450 publications. Dr. Lim is an IEEE Fellow and recipient of major awards including multiple Best Paper Awards (DAC 2023, TCAD 2022), and several Georgia Tech teaching honors. From 2022 to 2024, he served as a Program Manager at DARPA’s Microsystems Technology Office.

Abstract

• Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in Artificial Intelligence and Machine Learning that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of “scale-down and scale-out” that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. While, we have made progress towards this goal, the technologies we have developed have ridden on legacy packaging technologies making such systems incredibly complex and expensive to build. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically. There are many challenges in this approach. In this talk ,we will outline these challenges and show that the adoption of silicon like technology, new cooling and power delivery approaches, as well as aggressive connector technology, and design enablement, will propel packaging into the next dimension.

Biography

• Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. In 2023-4, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging.

Abstract

• The rapid evolution of the global semiconductor industry is closely aligned with the expansion of artificial intelligence (AI) capabilities across domains such as data centers, automotive systems, and high-performance computing (HPC). The unprecedented growth of data necessitates HPC platforms with enhanced power efficiency, bandwidth, and scalability. Consequently, micro-packaging technologies have advanced toward increasingly heterogeneous integration, supported by die-to-die interconnection platforms including 2.nD and 3D-IDM architectures. Furthermore, package platforms are transitioning toward higher substrate core counts and co-packaging with high-speed memory in order to meet the demands.
  Within this technological landscape, glass substrates are attracting significant attention as a next-generation packaging material. Compared with organic substrates, glass due to its material properties provides superior dimensional stability, low thermal expansion, improved electrical insulation, and enhanced mechanical robustness. These properties directly contribute to improved signal integrity, reduced warpage, and higher power delivery efficiency in advanced packaging systems. Particularly for HPC applications, glass substrates enable high-density input/output (I/O) interconnections and reliable die-to-die communication, thereby addressing the limitations of conventional packaging platforms.
  Recently glass substrate technologies emphasizes the development of fine-line lithography, advanced through-glass via (TGV) formation, low-resistance metallization, and panel-level manufacturing processes.
  These advances are essential to realize the dual goals of high-density interconnection and long-term reliability. At the same time, challenges remain in cost reduction, defect management, and process standardization, essentially necessarying the importance of coordinated efforts across academia, industry, and consortia.
  In conclusion, the adoption of glass substrates represents not only a technological advancement but also a paradigm shift in semiconductor packaging. By combining superior material properties with scalable manufacturing approaches, glass substrates are poised to play a pivotal role in enabling the next generation of HPC and AI-driven applications. Continued research, ecosystem collaboration, and strategic investment will be key to unlocking their full potential for sustainable innovation in the semiconductor industry.
  
  Keywords: High-Performance computing, Glass substrate, Semiconductor integration

Biography

• Education
  • Ph.D. & Post Doc., UC Berkeley ('98 ~ '11)
  • BS. & MS., Cornell University Electronic Engineering ('98)
• Career
  • ‘23.12 ~ Chief of Research Laboratory, Samsung Electro-Mechanics Corporate R&D Institute
  • ‘22.12 ~ ‘23.12 Head, S.LSI New Business TF, Semiconductor based Digital Healthcare
  • ‘18.07 ~ ‘22.11 Head, Meta/Si/Nano Optics & Optical/Bio Sensor, Samsung Advanced Institute of Technology
  • ‘11.06 ~ ‘18.06 Professor, Electrical Eng. and Medical Eng. Caltech